The RISC-V Reader: An Open Architecture Atlas
Product ID: 52044741
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The RISC-V Reader is a concise introduction and reference for embedded systems programmers, students, and the curious to a modern, popular, open architecture. RISC-V spans from the cheapest 32-bit embedded microcontroller to the fastest 64-bit cloud computer. The text shows how RISC-V followed the good ideas of past architectures while avoiding their mistake. Highlights include: Introduces the RISC-V instruction set in only 100 pages, including 75 figures An Instruction Translator Guide to help translate assembly language programs from ARM-32 and x86-32 instruction sets to RISC-V 2-page RISC-V Reference Card that summarizes all instructions 50-page Instruction Glossary that defines every instruction in detail 75 spotlights of good architecture design using margin icons 50 sidebars with interesting commentary and RISC-V history 25 quotes to pass along wisdom of noted scientists and engineers Ten chapters introduce each component of the modular RISC-V instruction set--often contrasting code compiled from C to RISC-V versus the older ARM, Intel, and MIPS architectures--but readers can start programming after Chapter 2. Praise for The RISC-V Reader: “This timely book concisely describes the simple, free and open RISC-V ISA that is experiencing rapid uptake in many different computing sectors.” Krste Asanovic, University of California, Berkeley, one of the four architects of RISC-V “I like RISC-V and this book as they are elegant—brief, to the point, and complete.” C. Gordon Bell, a computer architecture pioneer “ This handy little book effortlessly summarizes all the essential elements of the RISC-V Instruction Set Architecture, a perfect reference guide for students and practitioners alike.” Professor Randy Katz, University of California, Berkeley, one of the inventors of RAID storage systems “This clearly-written book offers a good introduction to RISC-V, augmented with insightful comments on its evolutionary history and comparisons with other familiar architectures.” John Mashey, one of the designers of the MIPS architecture “This book tells what RISC-V can do and why its designers chose to endow it with those abilities.” Ivan Sutherland, the father of computer graphics “RISC-V will change the world, and this book will help you become part of that change.” Professor Michael B. Taylor, University of Washington “This book will be an invaluable reference for anyone working with the RISC-V ISA.” Megan Wachs, PhD, SiFive Engineer Review: Essential reading and reference for the new-to-Risc-V world. - This book introduces and covers the RISC-V instruction set architecture in a comprehensive way. Regular comparisons are made with several ARM and x86 processor types. Many very useful program coding examples are provided. Plenty of architecture discussions such as how the RISC-V delivers shorter code sequences than ARM or x86 yet has less hardware to implement into CPU logic. Many advanced features explained. A comprehensive and useful 45 page listing of the instructions is provided. In total 180 pages of excellent RISC-V technical details. Review: Tremendous resource to have - This book is excellent if you're going to be doing anything in RISC-V assembly. Personally, I used it as a reference and to learn more about the design choices which were made when RISC-V was being developed. I left with a much greater appreciation of the elegance and careful design in the ISA. Note that if you're looking for an entry-level introduction to basic assembly concepts, you might struggle with this book a little. But if you've had some limited exposure to assembly before (for any architecture) you'll steam through the book.
| Best Sellers Rank | 580,696 in Books ( See Top 100 in Books ) 676 in Computer Hardware (Books) |
| Customer Reviews | 4.6 out of 5 stars 159 Reviews |
N**Y
Essential reading and reference for the new-to-Risc-V world.
This book introduces and covers the RISC-V instruction set architecture in a comprehensive way. Regular comparisons are made with several ARM and x86 processor types. Many very useful program coding examples are provided. Plenty of architecture discussions such as how the RISC-V delivers shorter code sequences than ARM or x86 yet has less hardware to implement into CPU logic. Many advanced features explained. A comprehensive and useful 45 page listing of the instructions is provided. In total 180 pages of excellent RISC-V technical details.
A**S
Tremendous resource to have
This book is excellent if you're going to be doing anything in RISC-V assembly. Personally, I used it as a reference and to learn more about the design choices which were made when RISC-V was being developed. I left with a much greater appreciation of the elegance and careful design in the ISA. Note that if you're looking for an entry-level introduction to basic assembly concepts, you might struggle with this book a little. But if you've had some limited exposure to assembly before (for any architecture) you'll steam through the book.
I**A
Good overview — for 2017
Interesting overview! Good overview of motivations, design approaches / philosophy, various available extensions, etc. As a software guy with limited ‘digital logic’ experience (VHDL courses in university and limited exposure to Verilog), I have approached the book with interest in organization of core RISC-V instruction set, naming conventions for extensions, basic approach to assembly, and potentially the ideas behind communications with ‘peripherals’ (memory, buses, etc) and less design of the cores. Organization of the book seems good as a reference, which is nice. There’s an overview of instructions, machine code representation, and the organization of the book is grouped by sets of instructions / extensions. Not important and thus doesn’t influence my impression, but there is something slightly off about the visual design — but nothing I can exactly point at and not crucial. One star goes off for nothing that’s the fault of the book, and one thing only: this is a 2017 title, and therefore a major reason why I was curious about RISC-V — vector extensions / RVV — couldn’t be covered because they didn’t exist yet. Since as of late 2025 RISC-V has been improving in important ways over the last few years, with usable products slowly appearing (dev products like Framework Laptop 13-sized mainboard, interesting products like Vega switch, etc), you may need an overview newer than this particular, well written book, which would teach you about important newer extensions that your physical hardware supports (or which it might not support, and you might want to find or produce core designs that do, as is the case with myself and RVV1.0 not being supported on 1st gen DC-ROMA board for Framework Laptop 13).
R**Y
Succinct and to the point
Great condition and one of the best processor architecture books I’ve read in a long time. Highly recommended.
M**N
Essential resource for an assembly programmer
I wondered about the wisdom of buying this - after all there is nothing in it that isn't available online. But I am very glad I did - the information is crisply and clearly presented and logically arranged. For an assembly programmer it's pretty much an essential resource. It won't teach you how to program in assembly, but if you have some assembly experience and are shifting to RISC-V this will almost certainly ease your path.
M**O
Good for SW but not for HW
Not really what I was expecting, maybe the title confused me. The book covers the RISCV different types of instructions and corresponding assembly language, shows the implementation of typical algorithms on RISCV as well as discusses the performance comparison of similar processors from different families. If the idea is to understand more about coding programs for the RISCV, specific instructions, and how they are compiled, then this is quite a good book. However, if you're looking for more details about the RISCV architecture and how instructions are executed on the hardware, you'll probably be a bit disappointed as it doesn't illustrate one sketch of the datapath or the control logic. In any case, if you're a CPU developer at some point it would be important to have a book like this.
M**N
Une introduction et une référence à la fois
Excellente introduction au jeu d'instruction RISC-V d'un côté et livre de référence de l'autre. On commence par le lire d'un bout à l'autre puis on continue à s'en servir comme référence. Le livre, dans sa préface, propose de soumettre les errata sur son site web où la liste des errata sera disponible aussi. Malheureusement ce n'est pas ou plus le cas. Il y a 2-3 petits typos que j'aurais voulu soumettre. Aussi j’apprécierais une nouvelle édition avec la version finale de l'extension RV ainsi que d'autres nouveauté introduites depuis 2017. Si une seconde édition voit le jour, je la commande immédiatement. D'ici là ça reste mon livre de référence. Lorsque ce livre ne suffit pas, c'est directement dans les spécifications ISA qu'il faut regarder. A recommander absolument.
W**D
Great reference!
This offers an exceptional introduction to the RISC instruction set. I've seen other reduced instruction set computers - RISCs in the generic sense or gRISCs for now - but I find this distinctive in several ways. Regularity and orthogonality are nearly defining features of gRISCs, and RISC-V shares that. It goes farther, though. RISC-V, like gRISCs ARM and MIPS, has a compressed instruction format. But, unlike the others, RISC-V compressed instructions form a proper subset of the full-length instructions - regularity of yet another kind. Also like others, different RISC-V implementations might omit or include parts of the instruction set. Unlike the others, though, RISC-V clearly defines subsets, like floating point or vector operations, making it a bit easier for programmers to remember what's supported in any specific implementation. The modular instruction set also makes it easy for chip builders to trade off features and performance against complexity and cost in predictable ways. As an aside, part of Patterson's reason for gRISC architecture in the first place was a belief that complex instruction sets were more likely to have instruction set bugs. A few high-profile cases, the Pentium FDIV bug being just one, certainly corroborate that belief. The more recent Spectre and Meltdown vulnerabilities, though not directly related to CISC vs. gRISC issues, also point out how increasing processor complexity increases the chance of implementation problems. I recommend this, not just to RISC-V programmers, but to anyone with an interest in modern processors. Although the RISC-V architecture is designed to be independent of any particular implementation, processor implementors will also find it very useful. -- wiredweird
A**E
Wouldn't have a degree without it.
Love the book, used it for my bachelor thesis (it was about writing a hardware abstraction library for a RISC-V processor). It was usable as a sort of quick reference as well as an introduction to RISC-V assembly. I have previous programming experience with some ARM assembly, so I can't tell how understandable it is for assembly beginners.
J**E
risc-v assembler
EL libro está bien pero está escrito como deprisa y corriendo y algunas cosas que son sencillas las convierten en complicadas. Necesitaría una segunda versión mejorada.
D**R
Gute, Kompakte Einführung mit Überdosis an Eigenlob
Ich arbeite gerade an einem Schachprogramm in Assembler für den 8-Bit Atmel-AVR. Ich wollte schauen wie einfach/kompliziert die Portierung auf einen RISC-V ist. Diese Frage wird im Buch kurz und bündig beantwortet. Es ist relativ trivial. Was - natürlich - nicht beantwortet wird sind die Feinheiten eines Entwicklungsboards. Die IO ist der nicht mehr so triviale Teil einer Portierung. Das habe ich auch nicht erwartet. Nicht so gut fand ich das dick aufgetragene Eigenlob. Die Autoren loben die genialen Ideen der RISC-V Architekten. Das sind sie selber. Sie zählen diverse Design-Sünden von anderen Architekturen auf (inkl. des eigenen MIPS) und betonen: Das gibt's bei RISC-V alles nicht. Man wird aber auch beim RISC-V im Laufe der Zeit solche Macken feststellen (falls der Prozessor alt wird). Das ist unweigerlich und ergibt sich auch aus der Weiterentwicklung der Technologie. Der MIPS delayed branch ist ein Beispiel dafür. Er ist für eine kurze Pipeline sinnvoll, wie diese länger geworden sind, ist er nur mehr ein pain-in-the-ass. Besonders Stolz sind sie auf das Fest-Verdrahten von Register-0 mit Null. Sie geben zahlreiche Beispiele wie sich daraus viele synthetische Befehle ergeben. Das ist allerdings ein uralter Trick. Ich reserviere auch in meinen Programm r0 mit Null. Man hat in der ISA alles Überflüssige weg gelassen. Teilweise dabei aber übers Ziel geschossen. Z.B. hat auch das Carry-Flag dran glauben müssen. Das ist ziemlich nützlich. Sehr fraglich ist auch die Idee, dass alle Immediate-Values immer sign-extended werden. Das ist z.B. bei der OR-Operation mit einem Immediate sehr unschön. Die Arbeitsgruppe von N. Wirth an der ETH hat den RISC-5 designed. Dieser gefällt mir von der ISA besser als sein römischer Nachkomme. Die Autoren betonen auch: Bei uns gibt es keinen Instruktions-Wildwuchs. Gleichzeitig definieren sie eine Reihe von Erweiterungen und stellen weitere vor die in der Pipeline sind vor. Ich habe den Eindruck: Der RISC-V ist weitgehend ein akademisches Produkt. Er hat bisher den ARM keine nennenswerten Martkanteile abgegraben. Es haben auch die FPGAs einen ARM als Hard-Prozessor eingebaut. Der RISC-V hat sich aber auch gegen die Softprozessoren MicroBlaze bzw. NIOS-II bisher nicht durchgesetzt. Auf Grund der Beschäftigung mit dem RISC-V baue ich gerade einen Softcore samt Assembler und Compiler für die XiLInx Artix-7 FPGA. Allerdings nehme ich den eleganteren RISC-5 der ETH und nicht den RISC-V als Vorlage.
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